1. Field of the Invention
The present invention relates to a method for producing a nonvolatile semiconductor memory device. More specifically, the present invention relates to a method for producing a nonvolatile semiconductor memory device having a metal-oxide-semiconductor (MOS) structure in which floating gates are provided so as to be isolated from each other by every bit.
2. Description of the Related Art
Referring to FIG. 3, FIGS. 4A to 4F and FIGS. 5A to 5F, a conventional process for fabricating a nonvolatile semiconductor memory device having an M0S structure will be described. This nonvolatile memory device includes first gates (or floating gates) and second gates (or control gates). The floating gates are provided so as to be isolated from each other by every bit.
FIGS. 4A to 4F and FIGS. 5A to 5F show cross sections of the nonvolatile semiconductor memory device corresponding to principal stages of the production process thereof. FIGS. 4A to 4F are cross-sectional views taken along the line X--X' shown in FIG. 3, while FIGS. 5A to 5F are cross-sectional views taken along the line Y--Y' shown in FIG. 3.
First, a field oxide film 31 having a thickness of about 300 nm is formed in an isolation region on a silicon substrate 21 doped with a P-type impurity in a low concentration by using a conventional technique. Thereafter, a tunneling oxide film 22 having a thickness approximately ranging from 8 to 13 nm is formed on an active region by a thermal oxidization method, as shown in FIG. 4A and FIG. 5A.
Next, a polysilicon film 23a having a thickness of about 100 to 300 nm is formed by a chemical vapor deposition (CVD) method so as to cover the tunneling oxide film 22, as shown in FIG. 4B and FIG. 5B. After the polysilicon film 23a is doped with an impurity (phosphorus) by an ion implantation method, the implanted impurity is activated by an annealing step. The implant dose is adjusted so that the concentration of phosphorus in the polysilicon film 23a is in the approximate range of 10.sup.19 to 10.sup.20 cm.sup.-3.
Then, stripe-shaped silicon portions 23b are formed from the polysilicon film 23a by conventional photolithography and etching techniques, as shown in FIG. 4C and FIG. 5C. These stripe-shaped silicon portions 23b are formed so as to cover the active region 32 in parallel to the region 32. Each stripe-shaped silicon portion 23b includes first portions to be used as a plurality of floating gates and second portions interposed between the adjacent first portions. The second portions of each stripe-shaped silicon portion 23b is etched by a later process step.
After an ONO film 24 (the thickness of an oxide film equivalent to the ONO film 24 is in an approximate range of 13 to 25 nm) is formed on the surface of each stripe-shaped silicon portion 23b by a thermal oxidization method, a CVD method or the like, a polycide film, i.e., a tungsten silicide film (WSi film) 26 and a polysilicon film (poly-Si film) 25 are formed so as to constitute a control gate 27, as shown in FIG. 4D and FIG. 5D.
Subsequently, a control gate 27 in a predetermined shape is formed from the polycide films 25 and 26 by conventional photolithography and etching techniques, as shown in FIG. 4E. Each control gate 27 extends over the substrate 21 so as to cross the plurality of stripe-shaped silicon portions 23b at a right angle. When the patterning of the control gate 27 is finished, the exposed portions of the ONO film 24 in the region which is not covered with the control gate 27 are removed and therefore the upper surfaces of the stripe-shaped silicon portions 23b are partially exposed. After the etching process is over, the exposed portions of the stripe-shaped silicon portions 23b are etched. By performing this etching process, a plurality of floating gates 23 are formed from each stripe-shaped silicon portion 23b so as to be isolated by every bit. This etching process is conducted by a highly anisotropic reactive ion etching (RIE) technology using plasma.
Then, impurity ions such as arsenic ions are implanted into the surface of the silicon substrate 21 by an ion implantation method, thereby forming source regions 29 and drain regions 30 in the respective active regions of the silicon substrate 21, as shown in FIG. 4F. This ion implantation is conducted by using the control gates 27 as masks, so that the impurity ions are not implanted into the active regions located under the control gates 27. As a result, N' type high-concentration impurity regions are formed in self-alignment with the control gates 27, so as to serve as the source regions 29 and the drain regions 30.
Thereafter, by using conventional photolithography and etching techniques, contact holes are provided through the oxide film with a thickness of about 400 nm formed by a CVD method or the like, thereby forming metal lines.
Data is written into the nonvolatile memory device by injecting electrons through the tunneling oxide film into the floating gates 23 by a hot electron injection method or a Fowler-Nordheim (FN) method and then by increasing the threshold voltage thereof. The written data is erased by pulling out the electrons injected into the floating gates 23 to the source regions 29 by an FN tunneling method, an ultraviolet ray irradiation method or the like and then by lowering the threshold voltage.
According to the conventional production method described above, the polycide film 27, the ONO films 24 end the stripe-shaped silicon portions 23b are continuously etched by the RIE method or the like after the control gate 27 is formed- Generally, the etching rates can not always be reproduced satisfactorily. In such a case, the etching rate may be varied among the respective etching processes. In addition, since multiple nonvolatile memory elements are simultaneously formed on a single substrate (or a silicon wafer) generally of a size. of several inches, the etching rates may be varied depending on the positions on the substrate. In consideration of the possible variation in the etching rates, the etching conditions to be actually employed are determined so that a larger amount of a film than the Mount calculated based on the thickness of the film to be etched and the etching rate is etched. For example, an "over-etching" is performed under a condition for etching an approximately ten-percent-thicker film than the film to be etched. In the case of conducting such an over-etching, the side walls (i.e., the portions B as shown in FIG. 6A) of each floating gate 23 and the portions of the tunneling oxide film 22 under both ends of the floating gate 23 (i.e., the portions a as shown in FIG. 6A) are much damaged by the irradiation during the time the RIE is performed, so that many defects are generated.
The defects generated in the portions of the tunneling oxide film 22 Just under both ends of the floating gate 23 become a major cause of lowering of the characteristics of a flash memory. For example, in a cell where defects are generated in an overlapped region between the source (not shown in FIG. 6A) of the tunneling oxide film 22 and the floating gate 23, an erasure rate may be excessively accelerated, so that an over-erased cell is possibly generated. If such an over-erased cell exists, then a data read can not be performed appropriately. Moreover, such defects may generate a hole trap level. In such a case, the holes generated by a tunneling phenomenon between the bands are captured by this hole trap level when the data is erased, so that the rewritability of the flash memory is degraded. Furthermore, when the defects are generated on the side walls of the floating gate 23, an oxide film damaged by a subsequent thermal oxidization process will exist. Accordingly, the electrons accumulated in the floating gate 23 can not be pulled out easily, and therefore the data storage property is disadvantageously degraded.
In addition, with respect to the etching process for forming the control gates 27, when the ONO film 24 is etched, the ONO film 24 on the side walls of the stripe-shaped silicon portion 23b is also required to be etched The ONO film 24 with a thickness substantially equal to that of the stripe-shaped silicon portion 23b is present on the side walls of the stripe-shaped silicon portion 23b in a direction vertical to the principal surface of the substrate 21. In order to remove the ONO film 24 completely, an over-etching is required to be performed at least by the amount corresponding to the thickness of the stripe-shaped silicon portion 23b. If such an over-etching is performed, then the exposed portions of the field oxide film 31 are also undesirably etched by an amount substantially corresponding to the thickness of the floating gate 23, as shown in FIG. 6B. This is because the etchant used for etching the ONO film 24 adversely etches the field oxide film 31. The thickness of the field oxide film 31 gradually decreases as the active region becomes closer to the film. Therefore, if the side walls of the stripe-shaped silicon portion are located over the regions of the field oxide film 31 where the thickness of he film is relatively small, then the etching of the ONO film 24 causes the exposure of the silicon substrate 21 under the field oxide film 31. Accordingly, the side walls of the stripe-shaped silicon portion 23b, i.e., the side walls of the floating gate 23, are required to be disposed where the thickness of the field oxide film 31 is larger than the amount to be removed of the field oxide film 31 when the ONO film 24 is etched. It is noted that FIGS. 6A and illustrating the problems of the conventional technologies, are cross-sectional views taken along the line Y.sub.2 --Y.sub.2 ' shown in FIG. 3.